Loongtion DDR3 DRAM chip: Integration and Selection Guide
A practical guide to selecting and integrating Loongtion DDR3 DRAM chip components for industrial embedded designs, covering produ...
Technical Resources
Selection guides, whitepapers, and engineering insights for industrial storage.
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44 items
Industrial SD and microSD Storage — Protocol and Selection Notes
A guide to SD and microSD card protocols, industrial-grade attributes, and key integration considerations for embedded system desi...
NOR Flash for Boot and Firmware Storage in Industrial Devices
A practical guide to using NOR Flash for boot and firmware storage in industrial embedded systems, covering execute-in-place (XIP)...
DDR Memory PCB Layout Best Practices for Rugged Systems
Practical layout guidelines for DDR3/4/5 in industrial and embedded systems, covering signal integrity, length matching, reference...
NVMe BGA SSDs for Solder-Down Embedded Storage: A Hardware Design Guide
A practical guide to integrating NVMe BGA SSDs into embedded designs, covering PCB layout, power sequencing, thermal management, a...
M.2 NVMe SSDs for Industrial Computing: A Selection Guide
Compare Loongtion M.2 NVMe industrial SSDs with DRAM cache. This guide focuses on the DRAM-cache series for peak performance in -4...
Integrating Industrial eMMC 5.1 in Embedded Systems: A Practical Guide
A step-by-step guide to integrating Loongtion Industrial eMMC 5.1 devices into embedded designs, covering hardware connections, in...
LPDDR4X for Low-Power Industrial Platforms: A Technical Guide
Explore how LPDDR4X memory meets the demands of space-constrained, battery-powered industrial devices. This guide covers electrica...
Wide-Temperature Industrial Storage — Common Engineering Questions
Engineering answers for wide-temperature (-40°C to +85°C) industrial memory and storage: NAND behavior, qualification testing, and...
What are the guidelines for trace impedance (e.g., 40Ω or 50Ω) for DDR3 signals and the required trace width for a given stack-up?
Practical answer covering common impedance targets for DDR3 and guidance on trace width based on stack-up, referencing JEDEC stand...
Is it acceptable to use through vias instead of blind or backdrilled vias for DDR3 routing to reduce PCB costs?
A practical field answer for engineers weighing cost vs. signal integrity: through vias can work for DDR3 if timing margins and st...
How do I compensate for an unbalanced number of vias in DDR3 routing, and what are the signal integrity implications?
Practical techniques to compensate for unbalanced vias in DDR3 PCB routing and the resulting signal integrity effects on timing, i...