Introduction
NOR Flash is a non-volatile memory technology uniquely suited for boot and firmware storage in industrial devices. Its random-access capability and support for execute-in-place (XIP) allow CPUs to read and execute code directly from the flash, eliminating the need to copy code to RAM at startup. This guide covers the fundamentals of NOR Flash, compares SPI and parallel interfaces, explains how XIP works, and discusses firmware update considerations for reliable industrial operation.
Understanding NOR Flash
NOR Flash is one of the two main Flash memory architectures (the other being NAND). It provides fast random read access, high reliability, and low bit-error rates, making it ideal for storing bootloaders, firmware, and configuration parameters. The table below compares NOR with other non-volatile memories.
| Memory Type | Characteristics | Pros | Cons | Typical Applications |
|---|---|---|---|---|
| **NOR Flash** | Random access, XIP support | Fast reads, high reliability | Small capacity, slow write/erase, higher cost | Bootloader, firmware storage |
| NAND Flash | Page access, block erase | Large capacity, low cost, fast writes | Bad blocks, requires ECC, no XIP | Mass storage (eMMC, SSD) |
| EEPROM | Byte-level erase/write | Byte-modifiable, long life | Small capacity, slow, high cost | Configuration parameters |
| SRAM / DRAM | Volatile, high speed | Very fast | Data lost on power off | System memory, cache |
SPI vs Parallel NOR Flash
NOR Flash originally used a parallel interface with separate address and data buses. Modern designs often use serial interfaces like SPI (Serial Peripheral Interface) or QSPI (Quad SPI) to reduce pin count and PCB complexity. The choice impacts performance, cost, and design effort.
Parallel NOR Interface
- Pin count: 40+ pins (address bus width depends on capacity)
- Bandwidth: High (e.g., 16-bit bus at 100 MHz yields ~200 MB/s)
- Access latency: Low, due to random access like SRAM
- PCB complexity: High, requires many traces and often more layers
- Typical use: High-performance XIP, network equipment, automotive dashboards
Serial NOR Interface (SPI/QSPI)
- Pin count: 6–8 pins (CS#, SCLK, MOSI, MISO, plus optional WP#, HOLD#)
- Bandwidth: Moderate (e.g., QSPI at 133 MHz yields ~66 MB/s)
- Access latency: Higher than parallel due to command overhead
- PCB complexity: Low, easy routing
- Typical use: IoT devices, wearables, consumer electronics, parameter storage
Comparison Table
| Feature | Parallel NOR | Serial NOR (SPI/QSPI) |
|---|---|---|
| Pin count | High (≥40) | Low (6–8) |
| PCB area & routing | Complex, large | Simple, small |
| Theoretical bandwidth | High (up to 200 MB/s) | Medium (up to ~66 MB/s QSPI) |
| Random access latency | Low (<150 ns) | Higher (due to command/address) |
| System cost | Higher | Lower |
| Typical applications | High-end XIP, networking | IoT, consumer, firmware |
| Driver complexity | Higher (memory controller) | Lower (standard SPI peripheral) |
Execute-in-Place (XIP)
XIP is a key advantage of NOR Flash. Because NOR provides random access like RAM, the CPU can read instructions directly from the flash without first copying them to RAM. This reduces memory requirements and speeds up boot time.
How XIP Works
The NOR Flash is mapped directly into the processor’s address space. When the CPU fetches an instruction, it reads from that memory region. The flash controller handles the bus protocol (parallel or serial) transparently.
Requirements for XIP
- Memory-mapped interface: The MCU/MPU must support mapping the flash into its address space (e.g., via FSMC for parallel, or QSPI memory-mapped mode).
- Low read latency: The flash must respond within the CPU’s wait states. Typical parallel NOR access times are 70–150 ns. For QSPI, clock frequency and dummy cycles must be managed.
- Code alignment: Code must be compiled to run from the flash address. Linker scripts should place text and read-only data in the flash region.
Benefits
- No need to copy bootloader to RAM, saving RAM and reducing startup time.
- Lower system cost (smaller RAM).
- Simplified design for deterministic boot.
Firmware Update Considerations
Updating firmware stored in NOR Flash requires careful planning to avoid bricking the device. Key considerations include:
Write/Erase Characteristics
- NOR Flash must be erased before writing. Erase is sector-based (typically 4 KB to 64 KB) and takes 100 ms to 2 s.
- Programming is page- or byte-oriented. A write-enable command must precede each erase or program command.
Reliability and Endurance
- Typical NOR Flash endurance: 100,000 erase/write cycles (for SLC). MLC/QLC have lower endurance.
- Data retention: >10 years at industrial temperature range.
- Bit errors are rare but possible; some systems include ECC or CRC checks.
Power Loss Protection
If power is lost during an erase or program operation, the flash may be left in an undefined state. Strategies to mitigate:
- Use a dual-bank approach: keep a golden copy in one bank, update the other. Switch banks only after successful verification.
- Implement power-loss detection and a backup power source (e.g., supercapacitor) to complete the current operation.
- Leverage the status register to check if a power-loss recovery is needed (e.g., using the DQ5 timeout flag).
Firmware Update Process (Simplified)
- Read the current firmware image and verify integrity.
- Send write-enable command to the flash.
- Erase the target sector(s).
- Program the new data page by page.
- Verify the written data (read-back and compare).
- If using dual-bank, update the active bank pointer.
- Reset and boot from the new firmware.
Selection Guide for Industrial NOR Flash
When selecting a NOR Flash for industrial boot/firmware storage, consider:
- Capacity: Bootloaders typically need 1 MB to 16 MB. Choose a device with room for future updates.
- Interface: QSPI is recommended for new designs due to good performance and low pin count. Use parallel only if latency requirements exceed what QSPI can deliver.
- Temperature range: Industrial grade (-40°C to +85°C) or extended (-40°C to +125°C) is essential for harsh environments.
- Reliability: Look for devices with built-in error detection and a proven track record in automotive/industrial applications.
- Write/erase performance: Consider the worst-case erase time; faster erases reduce update downtime.
For a wide selection of industrial-grade memory solutions, including NOR Flash, visit our industrial memory chips page or browse storage chips.
Conclusion
NOR Flash remains the go-to solution for boot and firmware storage in industrial devices due to its XIP capability, reliability, and simplicity. The choice between parallel and serial interfaces depends on performance and cost trade-offs. Understanding XIP requirements and planning robust firmware update procedures are critical for building reliable embedded systems. Loongtion offers a range of industrial memory products designed to meet these demands.