Is it acceptable to use through vias instead of blind or backdrilled vias for DDR3 routing to reduce PCB costs?

Is it acceptable to use through vias instead of blind or backdrilled vias for DDR3 routing to reduce PCB costs?

Routing DDR3 memory interfaces is a balance between signal integrity and board fabrication cost. While blind and backdrilled vias reduce stub length and improve high-speed performance, through vias are cheaper and often acceptable – provided the design respects DDR3 timing margins and layout constraints.

Signal integrity trade-offs

Through vias introduce a stub (the unused portion of the via barrel) that can cause reflections, impedance discontinuities, and resonant nulls in the insertion loss. For DDR3 data rates up to 2133 MT/s (1066 MHz clock), the stub length becomes critical when it exceeds about 50–100 mils (1.27–2.54 mm), depending on the stackup and data rate. Backdrilling removes the stub, while blind vias eliminate it entirely. Through vias without backdrilling keep the stub, which may degrade the eye diagram and reduce timing margins.

However, if the PCB is thin (e.g., 6–8 layers with total thickness <1.6 mm) and the DDR3 routing is on outer layers with short via spans, the stub length is small enough that through vias can be used without significant penalty. Many cost-sensitive designs (consumer, industrial control) successfully use through vias for DDR3 at 800–1600 MT/s.

What the datasheet tells you

For DDR3, the memory controller and DRAM datasheets specify timing parameters such as tIS (input setup time), tIH (input hold time), and output slew rates. These datasheets do not mandate a particular via type. The key is to ensure that the actual PCB routing meets the AC timing and signal quality requirements defined in the datasheets. For example, the output slew rate table in the DDR3 specification sets minimum and maximum slew rates that must be preserved at the DRAM pins – any via-induced degradation must still keep the signal within those limits.

While Loongtion's datasheets for industrial memory products (such as LPDDR4X) include similar electrical limits, the same principle applies to any DDR3 design: verify that your PCB meets the timing and signal quality requirements of the specific memory devices used.

Practical guidelines for using through vias

• Keep via stubs short: Place the signal via close to the target layer such that the unused portion is minimized. On a standard 8-layer board, routing a DDR3 signal on Layer 3 and terminating on Layer 6 leaves a stub through Layers 7–8; if possible, route on outer layers or use microvias for the last transition.
• Match impedance: Ensure the via diameter and antipad are designed for 40–60 Ω (single-ended) or 80–120 Ω (differential) to match the trace impedance. Use 3D field solvers to verify.
• Simulate the channel: Run IBIS or SPICE simulations of the entire path (driver → via → trace → via → receiver) including the DRAM model. Check that the eye height and width exceed the controller’s minimum requirements. Memory manufacturers often provide IBIS models upon request.
• Control layer transitions: Limit the number of vias per signal to two or three. Each via adds ~1–2 pF of capacitance and ~200–500 pH of inductance, which can accumulate.
• Use ground return vias: Place ground vias within 30–40 mils of each signal via to provide a low-inductance return path, reducing crosstalk and EMI.

When blind or backdrilled vias are strongly recommended

• Data rate ≥ 1866 MT/s (933 MHz clock) and board thickness > 1.6 mm.
• Multiple DDR3 ranks sharing a single bus (heavier loading).
• Designs with very tight timing budgets (e.g., <50 ps skew margin).
• Layouts where vias cannot be placed near the DRAM ball (long stub unavoidable).

In those cases, the incremental cost of backdrilling (typically 10–15% extra PCB cost) or blind vias (more expensive, but may reduce layer count) is justified by guaranteed signal integrity.

Conclusion

Through vias are acceptable for DDR3 routing in many cost-sensitive applications, especially at speeds ≤ 1600 MT/s and with careful stub management. The DRAM and controller datasheets provide the electrical limits; it is your responsibility to verify that your PCB design stays within them. For high-speed or heavily loaded designs, invest in backdrilling or blind vias to avoid expensive re-spins.

For more information on Loongtion's industrial memory products and support tools, visit our industrial memory chips page or browse the product category for detailed datasheets and application notes.