What are the guidelines for trace impedance (e.g., 40Ω or 50Ω) for DDR3 signals and the required trace width for a given stack-up?
The Loongtion DDR3 SDRAM datasheet does not specify PCB trace impedance values or trace width calculations. These design parameters are defined by the JEDEC DDR3 standard (JESD79-3) and your specific board stack-up. This answer provides practical guidance for engineers working with DDR3 interfaces.
Common DDR3 Impedance Targets
For a standard DDR3 interface, the following impedance targets are widely adopted:
| Signal Group | Target Single-Ended Impedance | Target Differential Impedance |
|---|---|---|
| DQ, DQS, DM | 50 Ω ±10% | 100 Ω ±15% (DQS pair) |
| Address/Command | 50 Ω ±10% | N/A |
| Clock (CK, CK#) | – | 100 Ω ±15% |
| Control (CKE, ODT, CS#) | 50 Ω ±10% | N/A |
Values outside these ranges (e.g., 40 Ω) are sometimes used for specific impedance-matching or power-integrity reasons, but 50 Ω is the typical single-ended target for DDR3. Always confirm with your PCB manufacturer and simulation results.
Determining Required Trace Width
Trace width is derived from the target impedance, PCB stack-up, and material properties. Use an impedance calculator (e.g., Polar Si9000, Saturn PCB Toolkit) with these inputs:
- Dielectric constant (εr) of the core and prepreg materials.
- Layer stack: reference plane distance (height to nearest solid plane), copper thickness, solder mask thickness.
- Trace geometry: microstrip (outer layer) or stripline (inner layer).
For a typical 4-layer board with 1 oz copper and FR4 (εr ~4.2), a 50 Ω microstrip trace might be around 0.18 mm (7 mil) wide with a 0.1 mm (4 mil) dielectric height. Your actual values will differ; always use the stack-up from your PCB vendor.
Practical Recommendations
- Simulate early: Run signal integrity simulations for your specific stack-up and impedance targets. DDR3 operates at up to 2133 MT/s, so sloppy impedance control can cause reflections and timing errors.
- Specify controlled impedance on your fab drawing: Indicate target impedance and tolerance (e.g., "50 Ω ±10% single-ended"). The fabricator will adjust trace width to meet the target.
- Match trace lengths: DDR3 requires length matching within groups (e.g., DQ within ±0.5 mm). Impedance is independent of length, but both matter.
- Use differential pairs for clocks and strobes: Maintain consistent pairing and keep pair-to-pair spacing > 3× the pair gap to minimize crosstalk.
When to Consider 40 Ω
Some systems use 40 Ω single-ended impedance for address/command signals to reduce overshoot or improve timing margins. This is not standard for DDR3 but can be evaluated with simulation. If your stack-up supports 40 Ω, adjust trace width accordingly (wider trace for lower impedance).
Loongtion DDR3 Products
Loongtion offers DDR3 SDRAM in 2Gb, 4Gb, and 8Gb densities with industrial temperature ranges. These devices are designed per JEDEC specifications and are compatible with standard DDR3 PCB design guidelines. For product details, visit the industrial memory chips landing page or browse the industrial products category.
Conclusion
Trace impedance for DDR3 is typically 50 Ω single-ended and 100 Ω differential, but your stack-up determines the exact trace width. The Loongtion DDR3 datasheet does not include layout rules; rely on JEDEC JESD79-3, your PCB fab, and signal integrity tools. For further assistance, contact Loongtion FAE with your specific stack-up and signal requirements.